ADSP-SC572 datasheet, dsp equivalent, Analog Devices

Features and benefits

Dual-enhanced SHARC+ high performance floating-point cores Up to 500 MHz per SHARC+ core Up to 3 Mb (384 kB) L1 SRAM memory per core with parity (optional ability to conf.

Application

SYSTEM CONTROL SECURITY AND PROTECTION SYSTEM PROTECTION (SPU) SYSTEM MEMORY PROTECTION UNIT (SMPU) FAULT MANAGEMENT AR.

Description

................................................. 3 ARM Cortex-A5 Processor ...................................... 5 SHARC Processor ................................................. 6 SHARC+ Core Architecture .................................... 8 S.

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